Automotive PCBs are becoming smaller while chip pin counts rise. When SoCs, MCUs, and FPGAs use dense BGA and QFN packages, large numbers of joints disappear beneath the device. Production testing that once touched a probe to each test point now faces a practical problem: there is nowhere to place the probe.
On March 23, 2026, German test-equipment manufacturer GÖPEL electronic expanded its product line with a CAN-FD/LIN BAC module for the SCANFLEX Multi Port Bus I/O Module 9305. The platform coordinates Boundary Scan, debug, programming, and automotive-bus interface function tests.
This looks like a module update, but reflects a common production challenge: as physical test points disappear, how can a manufacturer find open circuits, shorts, and defective solder joints on the board?
1. What Becomes Invisible to Traditional Probes?
Conventional ICT and Flying Probe testing are straightforward: a probe contacts pads or test points and measures voltage, resistance, or continuity, much like a technician checking points with a multimeter.
In a BGA, solder balls sit under the device. A QFN's principal pads are also concentrated under and around the package. Once the chip is mounted, an ordinary probe cannot directly contact those hidden connections.
The PCB is becoming denser too. High-speed signals, power networks, and more components leave little room for a test point on every net. Adding a pad or stub to some high-speed lines can disrupt impedance continuity and signal quality.
AOI checks placement, polarity, and visible joints. AXI images hidden joints under packages such as BGAs, but a visually normal image does not guarantee a correct electrical connection. ICT and Flying Probe make electrical measurements but require accessible locations.
Boundary Scan addresses the hidden digital-interconnect blind spot left among those methods.
2. Boundary Scan Is an Electronic Probe Inside the Chip, Not an X-Ray
Boundary Scan places test cells near the pins of a supporting IC rather than seeing through the device from outside.
During test, a controller shifts vectors through the TAP interface. One device drives specified logic levels, and cells in a neighboring device capture the result. If a logic 1 is expected but a 0 is read, the system can use net connectivity to investigate an open, short, missing resistor, or abnormal pull-up or pull-down.
IEEE 1149.1 defines the boundary-scan register and TAP access structure. Common signals include TDI, TDO, TCK, and TMS. Its value is the ability to test digital connections without an external probe touching every hidden pin.
Boundary Scan is not universal. Key devices must support it, and the manufacturer must provide a correct BSDL file describing test resources and pin mappings. Without a valid BSDL, the test may not be built; an erroneous file can create false results.
Standard Boundary Scan also shifts data serially and generally operates below the board's real functional speed. It is appropriate for static interconnect checks, not a substitute for high-speed signal integrity, protocol compliance, EMC, or full-system operating tests.
3. GÖPEL Adds CAN-FD/LIN for Interface Function Testing
GÖPEL's BAC module occupies one of five slots in the Multi Port Bus I/O Module 9305, adding CAN-FD and LIN interfaces to the SCANFLEX test system.
The company says SCANFLEX II provides 8 genuinely independent TAPs that can run in parallel at up to 100 MHz. The system can coordinate Boundary Scan, debug, programming, and CAN-FD/LIN interface function testing.
Two concepts must remain separate. Boundary Scan primarily asks whether digital connections among chips are miswired, open, or shorted. The CAN-FD/LIN BAC module asks whether the interface performs its intended communications function during production testing.
Adding BAC does not mean Boundary Scan itself suddenly performs complete automotive-bus validation. The 100 MHz figure is the TAP operating frequency, not a CAN-FD data rate, and is not equivalent to CAN protocol conformance, physical-layer signal quality, or vehicle-network certification.
Public information confirms the product function and platform combination. It does not establish deployment on a particular automaker's volume production line.
4. The BOM and PCB Design Determine Actual Coverage
Boundary Scan cannot be added casually after PCB release as production begins. Test capability has to be planned from the schematic and BOM as design for test, or DFT.
At least four questions need early answers:
- Do key MCUs, SoCs, and FPGAs support Boundary Scan, and are validated BSDL files available?
- Do the TAP chain, reset, boot mode, isolation devices, and connectors allow the tester to control the target board reliably?
- Do analog, power, and discrete networks without Boundary Scan retain necessary probe points or other measurement channels?
- Are CAN-FD, LIN, and similar interfaces tested functionally at real operating speed rather than only for static continuity?
A robust automotive PCBA test strategy layers methods: AOI checks appearance and polarity; AXI images hidden joints; Boundary Scan checks hidden digital interconnect; ICT or Flying Probe covers accessible analog and discrete networks; and function test verifies CAN-FD, LIN, power, and full-board operation.
No one method replaces the others; each covers what it does best.
Conclusion: Reduce Blind Spots, Not Every Probe
Boundary Scan is not new. Its value is increasing as BGA packages, complex SoCs, and dense PCBs spread: internal test structures can restore electrical visibility where physical probes can no longer reach.
GÖPEL's CAN-FD/LIN integration into SCANFLEX does not mean Boundary Scan replaces function test. It brings structural test, debug, programming, and interface verification toward one coordinated platform.
Automotive manufacturers should not ask only whether probes can be eliminated. They should ask whether test coverage is calculated early, failures can be isolated to a specific net, BSDL files and test programs can be maintained over time, and the added steps fit production takt time.
The denser the board, the less testing can be left until the last production step.
Disclaimer: This technical interpretation is based on public information for industry discussion only. It is not a basis for product selection, procurement, or quality disposition. Actual coverage depends on device BSDL files, PCB design, test programs, and production validation.