As AI chip power and transient current continue to rise, decoupling-capacitor selection is changing.
Engineers once started with required capacitance. As capacitors move closer to the chip, the question becomes whether that capacitance can deliver current to the die through a sufficiently short path at the moment the load demands it.
That is why low-ESL MLCCs, multiterminal capacitors, and silicon capacitors are all receiving attention. They are not competing for the entire capacitor BOM, but for the increasingly important final loop in a high-speed power-distribution network.
1. Why AI Chip Decoupling Cannot Be Selected by Capacitance Alone
In an ideal model, a larger capacitor stores more charge. A real capacitor also has ESR and ESL, plus interconnect parasitics from pads, traces, vias, and the package substrate.
As frequency rises, inductive reactance increases according to (X_L = 2πfL). Even when nominal capacitance is unchanged, a long power and return path can prevent the capacitor from operating effectively in the target band.
One PDN therefore uses multiple device layers. Conventional MLCCs provide board-level bulk and general decoupling. Reverse-geometry, three-terminal, and other low-ESL MLCCs handle local high-frequency decoupling near the load. As placement moves into the package substrate, next to the die, or into a height-constrained region, device thickness, terminal organization, and the installed current loop carry more weight—and silicon capacitors gain value.
2. Two Main Low-ESL Routes Are Emerging in China
On the ceramic route, EYANG uses three-terminal MLCCs for board filtering and near-load decoupling, while ViiYong's MLCF uses four external electrodes for PMIC noise suppression. Overseas suppliers including TDK and Murata have established reverse-geometry, three-terminal, and low-ESL MLCC lines. These devices preserve MLCC advantages in capacitance, mounting, and supply while improving board-level high-frequency loops.
Silicon-capacitor vendors focus more heavily on near-die placement and package integration. FoinMicro HDC1 uses 3D TSV and high-k deep-trench technology, while Murata/IPDiA UESL targets under-BGA and embedded use with thickness around 85 μm. Launchip's LHC family turns the multiterminal concept into defined devices with 2, 7, 12, and 49 terminals and representative thicknesses of 70-100 μm for near-die PDN and advanced-package decoupling in AI and HPC.
Because capacitance, mounting, and ESR/ESL measurement methods differ among vendors, the figure is not a performance ranking. It illustrates different routes to lower parasitics: ceramic internal structures, three-terminal feedthrough filtering, and ultrathin silicon devices with terminal arrays placed closer to the die. Launchip's differentiation should be understood in that engineering context.
3. Both Are 100 nF: What Separates Launchip's 2- and 7-Terminal Devices?
Two 100 nF Launchip products provide a direct view of terminal structure. LHC104SA2K0042 has 2 terminals and LHC104SA2K0047 has 7. Both are rated at 1.2 VDC with breakdown voltage of at least 4.0 VDC. Their footprints are similar at approximately 0.64 × 0.34 mm and 0.65 × 0.35 mm.
The major difference is terminal organization. The 2-terminal device has one VDD and one VSS connection. The 7-terminal device uses 4 VDD and 3 VSS terminals, interleaving supply and return so current can enter through more parallel paths.
According to Launchip specification V1.3, the 2-terminal device has typical ESR of 90 mΩ, maximum ESL of 120 pH, and typical thickness of 100 μm. The 7-terminal device specifies 16 mΩ, 15 pH, and 70 μm, respectively.
Using only the data-sheet ESL limits for dimensional illustration, inductive reactance at 1 GHz is approximately 0.75 Ω for 120 pH and 0.094 Ω for 15 pH. Those are not complete device impedances and do not replace board-level measurement, but they explain why equal nominal capacitance does not imply equal near-die high-frequency performance.
This is not a strict single-variable experiment in terminal count because the devices also differ slightly in thickness and dimensions. It nevertheless shows that multiterminal design is not simply adding solder points to a conventional capacitor; it reorganizes the supply and return paths.
Low ESL is not unique to silicon. TDK reverse-geometry MLCCs, Murata LLL products, and domestic three-terminal MLCCs also reduce parasitics. What makes Launchip noteworthy is a complete 2- and 7-terminal pair with equal capacitance and similar dimensions, allowing direct evaluation of the terminal structure instead of presenting one isolated typical ESL value.
4. Launchip Extends Beyond One 7-Terminal Product
One 7-terminal sample would be a technology demonstration. Launchip's portfolio instead shows a structural progression from 2 to 49 terminals.
At 200 nF, LHC204SA2K0032 and LHC204SA2K0037 provide 2- and 7-terminal structures. LHC354SA7K003C increases to 12 terminals at 350 nF. LHC205SA8K003ZC uses a 7 × 7 array with 28 VDD and 21 VSS terminals and reaches 2 μF.
The devices do not have identical capacitance, dimensions, or placement, so the range should not be reduced to "more terminals are better." It demonstrates structural options for different near-die PDN positions: conventional dual-terminal access, interleaved multipoint access, and dense VDD/VSS arrays selected according to transient current, height, and assembly method.
Launchip's May 2026 catalog lists the representative devices above as in mass production and provides complete part numbers, pin definitions, and package dimensions. Some are offered in tape-and-reel, blue film, or wafer delivery. A portfolio combining same-capacitance structural pairs, a 2- to 49-terminal progression, and representative thicknesses of 70-100 μm is more useful for engineering evaluation than one highlighted ESL number.
Conclusion: Silicon Capacitors Compete for the Position Closest to the Die
As AI chip PDNs move toward higher transient current and lower target impedance, capacitor selection can no longer stop at capacitance, voltage, and case size. Placement, supply and return entry, and loop length directly affect high-frequency decoupling.
Conventional MLCCs remain the main source of board-level capacitance and general decoupling. Three-terminal, reverse-geometry, and low-ESL MLCCs provide local optimization near the load. Multiterminal silicon capacitors target critical positions in the package substrate, adjacent to the die, and under tight height limits.
Launchip does not claim to replace every MLCC. It has built a clear product progression for this critical location: direct 2- and 7-terminal comparisons at the same capacitance, 12- and 49-terminal arrays, and ultrathin 70-100 μm devices.
As a capacitor moves from the PCB toward the die, the calculation changes from how much capacitance is needed to how many paths deliver current and where they deliver it. That is the engineering significance of Launchip's multiterminal silicon capacitors.
Original-content notice: Launchip Technology supplied the product data used in this article in August 2026. Please credit “Launchip Technology” when reproducing the associated data or images.
