What matters most in an AI chip? Some would say the process node, others compute performance, and others HBM. But if the compute chiplets, HBM, and silicon interposer cannot be packaged together on schedule, the trillions of operations on the data sheet can only process empty air in a warehouse.
NVIDIA Blackwell Ultra links two compute dies, each close to the reticle-size limit, into one GPU with 10 TB/s of die-to-die bandwidth; some models carry as much as 288 GB of HBM3E. AMD's MI300X looks more like a chip apartment building, integrating 8 XCDs, 4 IODs, and 8 HBM3 stacks in one device for 192 GB of capacity and 5.3 TB/s of peak bandwidth.
Are these still single chips? To the system, yes. From a manufacturing perspective, they are teams. Competition in AI silicon is shifting from who can pattern the most advanced transistors to who can reliably assemble a group of expensive chiplets into one system.
01. Why Split a GPU into More Than a Dozen Pieces?
A chip does not become more advanced simply by being divided into more pieces. The problem is that a larger monolithic die approaches the reticle-size limit, reducing wafer utilization and increasing yield pressure. A single defect can destroy the entire large die. Chiplets allow compute, I/O, cache, and other functions to use different processes before advanced packaging recombines them.
It is similar to constructing a building. Instead of casting everything as one structure, the kitchen, bedroom, and living room are prefabricated separately and assembled on site. Prefabrication can reduce some manufacturing difficulty, but shifts the burden to the assembly team: interfaces must align, power domains must cooperate, signals must not take unnecessarily long paths, and thermal design cannot be handled independently.
A 2.5D package generally places compute chiplets and HBM side by side on a silicon or RDL interposer, as if they occupy one floor connected by high-speed roads beneath them. A 3D package stacks chiplets vertically and connects them through microbumps or hybrid bonding, moving from a flat layout to a multistory one.
Do more floors and more valuable occupants make the assembly team less important? The opposite is true. Chiplets do not reduce the value of packaging. They move interconnect, power-delivery, and yield problems that once lived inside the chip into the package in bulk.
02. Why Can 2.5D and 3D Packaging Constrain AI Chip Deliveries?
From top to bottom, a typical AI accelerator BOM may contain a heat sink or cold plate, compute chiplets, HBM stacks, microbumps, a silicon or RDL interposer, C4 bumps, an ABF package substrate, BGA balls, and the accelerator-card PCB. None of those layers is merely an enclosure.
Compute chiplets and HBM need dense interconnects. The interposer carries large numbers of high-speed signals. The ABF substrate connects the package to the PCB, and the thermal system removes hundreds of watts or more. Warpage, thermal stress, signal integrity, power noise, and system test can each reduce total package yield.
The phrase "HBM packaging" can itself refer to two different processes. One stacks multiple DRAM dies into HBM using TSVs, microbumps, and related techniques. The other integrates completed HBM stacks with a GPU or ASIC on an interposer and package substrate. Mastery of the first does not establish the ability to complete the second.
TSMC CoWoS is not one universal solution. CoWoS-S uses a silicon interposer; CoWoS-R emphasizes an RDL interposer; and CoWoS-L introduces local silicon interconnect. A CoWoS-L package at 3.5 times reticle size is in production, a 5.5-times-reticle version is planned to complete qualification in 2026, and a 9.5-times-reticle roadmap remains under development.
Packages are growing because there are more GPU chiplets, more HBM stacks, and more complex interconnect and power delivery. Advanced packaging adds more than processing cost: it increasingly controls whether the complete AI device can ship.
03. Tongfu Is in Trial Production; Why Has JCET Not Announced Volume HBM Deliveries?
Chinese companies all discuss advanced packaging, but they are not necessarily at the same stage. Mixing research, trial production, mass production, and customer supply creates an exciting article but a confusing procurement decision.
Tongfu Microelectronics has disclosed total investment of approximately RMB 1.059 billion in a project for high-bandwidth memory chiplet advanced-packaging technology and line construction. Designed annual capacity is 36,000 wafers, corresponding to 2 million high-bandwidth memory chiplet products. Public materials from January 2025 described the project as being in trial production and not yet accepted.
Trial production means the line is real and equipment is operating. It does not mean stable mass production, actual shipments of 2 million units, or formal customer adoption. Designed capacity is a plan; actual output still has to pass acceptance, ramp, yield, and order tests.
In 2026, Tongfu proposed investing approximately RMB 888 million in another project to increase memory-chip assembly and test capacity, with a three-year construction period. Review materials assume that the project will add capacity of 849,600 wafers after reaching full production in 2029, but it covers FLASH, DRAM, and other memory products. Treating all 849,600 wafers as HBM would trade factual accuracy for clicks.
JCET is in a different position. Its disclosed portfolio includes XDFOI, 2.5D/3D, high-density memory, and high-performance-computing packaging, and it continues to expand advanced capacity. Yet when investors asked directly about HBM assembly, test, and orders, the company emphasized experience in DRAM and Flash packaging and an intention to strengthen advanced memory packaging. It did not explicitly confirm volume HBM delivery.
Why not announce HBM production on the company's behalf? Possessing an advanced-packaging platform, participating in the memory market, and winning volume HBM orders are three different scorecards.
04. Silicon Interposers Are in Volume Production. Does That Complete a Domestic CoWoS Alternative?
China has made tangible progress in silicon interposers, with specific platforms rather than only research terminology.
Prospectus materials from SJ Semiconductor say that SmartPoser-Si, based on a through-silicon-via interposer, has entered volume production; SmartPoser-RDL, based on organic RDL, is in low-volume trial production; and SmartPoser-BD, using an embedded silicon bridge, has completed full-process validation. The company also disclosed that it developed a next-generation 2.5D microbump process with 20 μm pitch during 2023-2025 and established core HBM test technology in 2023.
That is a meaningful milestone. It shows that domestic silicon interposers have advanced from a laboratory concept to defined manufacturing platforms. It does not mean that a complete AI GPU-and-HBM package is already solved.
Full delivery still requires an HBM source, compute chiplets, microbumps, an ABF substrate, very-large-format packaging, thermal materials, test equipment, and system customers. Advanced-package yields multiply rather than simply add: the compute die, interposer, and HBM may all be known good, yet the combined package can still fail because of warpage, bonding, or thermal stress.
A failed conventional component may cost a few yuan. A late-stage failure in a package containing multiple HBM stacks and valuable compute chiplets creates a loss on a completely different scale. A sample is the admission ticket; stable delivery lot after lot is the real industrial barrier.
Conclusion: Advanced Packaging Is Becoming a Second Front End
Advanced packaging was traditionally called the back end because it followed wafer fabrication. But if chiplet partitioning, interconnect, HBM count, power architecture, and thermal design must all be co-designed from the beginning, can it still be treated as only a back-end process?
It is more useful to think of it as the AI chip's second front end. It does not fabricate all the transistors, but it determines whether those transistors become a testable, coolable, manufacturable, and deliverable device.
The domestic supply chain has made visible progress: Tongfu's high-bandwidth-memory chiplet project reached the trial-production stage described in public materials; JCET continues to build XDFOI, 2.5D/3D, and high-density-memory capabilities; and SJ Semiconductor's SmartPoser-Si has entered volume production.
The questions for buyers and industry observers are not whether projects exist, but whether there is a defined volume product, data for total-package yield and reliability, repeated lot delivery, and formal evidence of customer adoption.
Every vendor can announce expansion. The company that can ship an expensive GPU, its HBM, and its interposer together and intact is the company that truly gains influence over advanced AI packaging.
Disclaimer: This article is compiled from public information for industry discussion only. It does not constitute investment, procurement, or part recommendations. Product status and supply relationships are subject to the latest formal company disclosures.